LOGIC-TIMING SIMULATION AND THE DEGRADATION DELAY MODEL
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LOGIC-TIMING SIMULATION AND THE DEGRADATION DELAY MODEL
by Manuel J Bellido, Jorge Juan & Manuel Valencia (University of Seville, Spain & Institute for Microelectronics of Seville, Spain)
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the �Degradation Delay Model�, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.
Contents:
- Fundamentals of Timing Simulation
- Delay Models: Evolution and Trends
- Degradation and Inertial Effects
- CMOS Inverter Degradation Delay Model
- Gate-Level DDM
- Logic Level Simulator Design and Implementation
- DDM Simulation Results
- Accurate Measurement of the Switching Activity
View Full Text (9,859 KB)
Readership: Senior researchers, industrial developers, postgraduate and
graduate students in electrical & electronic engineering and computer engineering.
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288pp
Pub. date: Nov 2005
eISBN 978-1-86094-736-0
Price: US$55
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